タイトル |
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An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors
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作成者 |
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Takamaeda-Yamazaki, Shinya
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アクセス権 |
open access |
権利情報 |
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Copyright ©2017 The Institute of Electronics, Information and Communication Engineers
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主題 |
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Other
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dynamic branch prediction
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supervised machine learning
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naive Bayes classifier
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energy-efficient microprocessor
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low-power architecture
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CMOS digital circuit
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NDC
540
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内容注記 |
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Abstract
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In this paper, we propose a Bayesian branch-prediction circuit, consisting of an instruction-feature extractor and a naive Bayes classifier (NBC), as a machine learning approach for branch prediction. A branch predictor predicts the outcome of a branch instruction by analyzing the pattern of the previous branch outcome. In other words, branch prediction can be viewed as a type of pattern recognition problem, and such problems are often solved using neural networks. A perceptron branch predictor has already been proposed as one example of a neural branch prediction architecture, which predicts the next branch outcome by using past branch history to form feature vectors. The proposed circuit is constructed by replacing the arithmetic unit (neurons) in conventional neural branch predictors with an NBC. By introducing an approximate Bayesian computation and its parallel architectures, the NBC circuit completes branch prediction within two clock cycles per instruction. This constitutes a suitable replacement for conventional branch predictors in modern pipelined reduced instruction set computing microprocessors.
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出版者 |
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電子情報通信学会
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The Institute of Electronics, Information and Communication Engineers / IEICE
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日付 |
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言語 |
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資源タイプ |
journal article |
出版タイプ |
VoR |
資源識別子 |
HDL
http://hdl.handle.net/2115/68659
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関連 |
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isIdenticalTo
DOI
https://doi.org/10.1587/nolta.8.235
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収録誌情報 |
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Nonlinear Theory and Its Applications, IEICE
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巻8
号3
開始ページ235
終了ページ245
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ファイル |
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fulltext
8_235.pdf
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978.6 KB
(application/pdf)
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コンテンツ更新日時 |
2023-07-26 |