Title |
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ja
電子工学実験におけるFORTHの利用
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en
FORTH based logic circuits laboratory work
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Creator |
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ja
齋藤, 正和
ja-Kana
サイトウ, マサカズ
en
Saito, Masakazu
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ja
藁科, 崇
ja-Kana
ワラシナ, タカシ
en
Warashina, Takashi
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ja
高橋, 光生
ja-Kana
タカハシ, ミツオ
en
Takahashi, Mitsuo
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ja
田中, 清臣
ja-Kana
タナカ, キヨオミ
en
Tanaka, Kiyoomi
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Description |
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Abstract
The purpose in the laboratory experiments of logic circuits design, is students to study how tocarry out the software design and hardware design according to each function, and evaluate thedesign in consideration of the trade-off problem.Therefore, paying attention to the modularity and hierarchy of logic circuits design, studentsassemble and test logic circuits, and they study design know-how about logic circuits.As FORTH system has an interactive programming environment and its modularity is suitable toreplace hardware function by software function, we adopt FORTH system for logic circuitslaboratory work.In this paper, new experiment environment of logic circuits design using FPGA, and laboratorywork tools by FORTH system are presented.
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Publisher |
電気通信大学
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Date |
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Language |
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Resource Type |
departmental bulletin paper |
Version Type |
VoR |
Identifier |
URI
https://uec.repo.nii.ac.jp/records/6821
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Journal |
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ja
電気通信大学紀要
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Volume Number16
Issue Number2
Page Start179
Page End184
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File |
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Oaidate |
2024-03-08 |